1. Field of the Invention
The present invention relates to an output circuit. More particularly, the present invention relates to an output circuit having a CMOS configuration.
2. Discussion of the Related Art
Conventional output circuits having a CMOS configuration, which have been used for synchronous rectification type step-down DC-DC converters, have the following drawback. Specifically, when a control signal is input to gates of a PMOS transistor and a NMOS transistor, which gates are connected with each other, and the control signal changes from a low level to a high level or vice versa, there is a period in which both the PMOS transistor and NMOS transistor are in an ON state at the same time, resulting in flow of a large current therethrough (hereinafter referred to as a through current or a through current problem). Thereby, problems in that the consumption current seriously increases and a large noise is produced in the power source are caused.
In attempting to prevent occurrence of the through current problem, such an output circuit as illustrated in FIG. 1 is used. FIG. 2 is a timing chart illustrating the waveforms of voltage at several portions of the circuit illustrated in FIG. 1.
Referring to FIG. 2, a character IN denotes a level (i.e., a high level H or a low level L) of the input terminal of the circuit; a character PH denotes the gate voltage of a PMOS transistor M101; a character A denotes an input signal input to a second input terminal of a NAND circuit 114; a character B denotes an input signal input to a second input terminal of an NOR circuit 111; a character NL denotes a gate voltage of a NMOS transistor M102; a character M101 denotes an ON or OFF state of the PMOS transistor M101; a character M102 denotes an ON or OFF state of the NMOS transistor M102; and a character OUT denotes a level (i.e., a high level H or a low level L) of the output terminal OUT of the output circuit.
When the input terminal IN is on a low level L, the output signal of the NAND circuit 114 is on a high level. Therefore, the output signal output from an inverter 115 is on a low level and the gate voltage NL of the NMOS transistor M102 is on a low level. Therefore, the NMOS transistor M102 is in an OFF state. In addition, since the gate voltage NL of the NMOS transistor M102 is on the low level, the input signal B input to the second input terminal of the NOR circuit 111 attains a low level, and the output signal output from the NOR circuit 111 attains a high level. Further, since the output signal output from an inverter 112 is on a low level, the gate voltage PH of the PMOS transistor M101 is on a low level. Therefore, the PMOS transistor M101 is in an ON state. Furthermore, since the gate voltage PH of the PMOS transistor M101 is input to the second input terminal of the NAND circuit 114 via a buffer circuit 113, the input signal A input to the second input terminal of the NAND circuit 114 is on a low level.
When the input terminal IN attains a high level H, the output signal from the NOR circuit 111 attains a low level, and the output signal from the inverter 112 attains a high level. In this regard, a gate capacitance of the PMOS transistor 101 is charged, and thereby it takes a certain time until the gate voltage PH of the PMOS transistor M101 attains a high level as illustrated in FIG. 2. When the gate voltage PH of the PMOS transistor M101 reaches a half voltage (i.e., Vdd/2) of a power supply voltage Vdd, the output signal A from the buffer circuit 113 inverts and attains a high level. In this regard, a capacitor C101 is charged, and thereby the output signal A from the buffer circuit 113 gradually increases as illustrated in FIG. 2.
When the gate voltage PH of the PMOS transistor M101 increases and exceeds a threshold voltage Vtp, the PMOS transistor M101 achieves an OFF state. At this time, the input signal A has not yet reached the half voltage Vdd/2, and the gate voltage NL of the NMOS transistor M102 is still on the low level. Therefore, the NMOS transistor M102 maintains the OFF state. Accordingly, production of a through current can be prevented.
When the voltage of the output signal from the buffer circuit 113 further increases and reaches the half voltage Vdd/2, the output signal from the NAND circuit 114 attains a low level and thereby the output signal from the inverter 115 attains a high level. In this regard, the gate capacitance of the NMOS transistor M102 is charged, and thereby the gate voltage NL of the NMOS transistor M102 gradually increases as illustrated in FIG. 2. When the gate voltage NL of the NMOS transistor M102 reaches a threshold voltage Vtn, the NMOS transistor M102 achieves an ON state. When the gate voltage NL further increases and reaches the half voltage Vdd/2, the output signal from the buffer circuit 116 attains a high level. In this regard, a capacitor C102 is charged, and therefore it takes a certain time until the input signal B attains a high level as illustrated in FIG. 2. Even when the input signal B input to the second input terminal of the NOR circuit 111 attains a high level, the output signal from the NOR circuit 111 does not change because the input signal IN is already on the high level H.
When the input terminal IN attains the low level, the output signal from the NAND circuit 114 attains the high level, and the output signal from the inverter 115 attains the low level. In this regard, the gate capacitance of the NMOS transistor M102 is discharged, and therefore it takes a certain time until the gate voltage NL attains a low level. When the gate voltage NL of the NMOS transistor M102 decreases and reaches the half voltage Vdd/2, the output signal from a buffer circuit 116 inverts and attains a low level. In this regard, the capacitor C102 is discharged, and therefore it takes a certain time until the output signal B attains the low level as illustrated in FIG. 2.
When the gate voltage NL of the NMOS transistor M102 decreases and reaches the threshold voltage Vtn, the NMOS transistor M102 achieves the OFF state. At this time, the voltage of the input signal B has not yet decreased to the half voltage Vdd/2 and the gate voltage PH of the PMOS transistor M101 is still on the high level. Therefore, the PMOS transistor M101 maintains the OFF state. Thus, production of a through current can be prevented even when the input terminal IN changes to the low level L.
Further, when the voltage of the input signal B decreases and reaches the half voltage Vdd/2, the NOR circuit 111 attains the high level and the output signal from the inverter 112 attains the low level. In this regard, the gate capacitance of the PMOS transistor M101 is discharged, the gate voltage PH gradually decreases as illustrated in FIG. 2. When the gate voltage PH decreases and reaches the threshold voltage Vtn, the PMOS transistor M101 achieves the ON state. When the gate voltage PH further decreases and reaches the half voltage Vdd/2, the output signal from a buffer circuit 113 attains a high level. In this regard, the capacitor C101 is charged, and therefore it takes a certain time until the output signal A attains the low level as illustrated in FIG. 2. When the output signal from the buffer circuit 113 attains the low level, the input signal A to the NAND circuit 114 attains a low level but the output signal from the NAND circuit 114 is not changed because the input terminal IN is already on the low level.
Thus, it is impossible for the circuit illustrated in FIG. 1 that both the PMOS transistor and the NMOS transistor are on the ON state at the same time when the level of the signal input to the input terminal IN changes. Therefore, production of a through current can be prevented. However, occurrence of the problem in that both the PMOS transistor and the NMOS transistor are on the ON state at the same time is prevented by using a delay circuit utilizing the output current of the buffer circuit 113 and charging and discharging of the capacitor C101, and utilizing the output current of a buffer circuit 116 and charging and discharging of the capacitor C102. Therefore, it is necessary to set the delay time of the delay circuit to be longer than the times in which the PMOS transistor M101 and the NMOS transistor M102 are on the ON state. Therefore, the output circuit cannot perform high speed processing. In order to shorten the delay time, the precision of the delay time has to be enhanced. Specifically, since it is necessary for the output circuit to use a regulator circuit for trimming, etc., the area of the chip increases, resulting in increase of manufacturing costs of the output circuit because additional manufacturing processes are necessary.
In attempting to remedy the drawbacks, published unexamined Japanese patent application No. 2000-49586 discloses an output circuit without a delay circuit, which is illustrated in FIG. 3.
In the output circuit illustrated in FIG. 3, reference voltages Vthp and Vthn are set to be not greater than the threshold voltage of the PMOS transistor M101 and the threshold voltage of the NMOS transistor M102, respectively. The gate voltage PH of the PMOS transistor M101 is compared with the reference voltage Vthp by a comparator 124. When the gate voltage PH reaches the voltage at which the PMOS transistor M101 achieves an OFF state, the comparator 124 outputs a high level signal to open the gate of an AND circuit 125. In addition, the gate voltage NL of the NMOS transistor M102 is compared with the reference voltage Vthn by a comparator 126. When the gate voltage NL reaches the voltage at which the NMOS transistor M102 achieves an OFF state, the comparator 126 outputs a high level signal to open the gate of a NAND circuit 123. Thus, occurrence of the problem in that both the PMOS transistor and the NMOS transistor are on the ON state at the same time can be prevented, resulting in prevention of production of a through current.
However, the output circuit illustrated in FIG. 3 has a drawback in that since two reference voltages are set and two comparators are used, the size of the circuit increases, resulting in increase of the size of the chip, thereby increasing the manufacturing costs of the circuit.
Because of these reasons, a need exists for an output circuit, which can perform high speed processing without increasing the chip size.